Mapping Pins and Programming FPGA

From FPGA Wiki

Data that is to be displayed on the LEDs of the Spartan 3E must be made available as an output signal in the top-level component of the project. Generally, the data-types for output will be std_logic and std_logic_vector. Any integers must first be converted to one of these types before being pin-mappable. Similarly, data can be set to the datapath with input signals in the top-level component.

Contents 1 Adding Output Signals 2 Mapping to Pins 3 Configuring the Target Device 4 Programming the FPGA

Adding Output Signals

In the top level component of the Xilinx project, add output ports for each signal that should be displayed on LEDs. For example, if a certain register should have it's value (or at least lowest 8 bits since there are only 8 LEDs) displayed, that register must be routed out of the register unit to the top-level component and finally to the output ports. An example top-level component which will output the value of register 1 is shown below:

entity mips_datapath is
	port (
		clk_in : in std_logic;
		output : out std_logic_vector(31 downto 0)
	);
end mips_datapath;

architecture structural of single_cycle is
-- ... snip...
begin
	reg_file: register_file_component port map( ..., register_1_value => output);
end structural;

Notice there is an out-port in the register component itself that makes the value of register 1 available to higher level components (in this case the top-level).

Mapping to Pins

Now that the top-level component has output signal(s) to be displayed, they can be mapped to pins on the FPGA. In this example, we will map the lowest 8 bits of the output port (register 1 value) to the 8 LEDs on the Spartan 3E. Additionally, we will map the clk_in input port to the onboard 50 MHz clock.

Begin by selecting the top-level component in the left pane of Xilinx. Then, in the processes pane, navigate to User Constraints -> Floorplan Area / IO / Logic - Post-Synthesis. This will cause the project to be re-built and then open a new window titled "Xilinx PACE" that looks like:

On the left, notice that all of the in- and out-ports for the top-level component are listed along with their direction. Mapping these to pins on the FPGA simply involves entering the pin locations in the "Loc" column. For the Spartan 3E:

• 50 MHz clock: C9
• LED0 (rightmost): F12
• LED1: E12
• LED2: E11
• LED3: F11
• LED4: C11
• LED5: D11
• LED6: E9
• LED7 (leftmost): F9

Map the corresponding bits of the output ports to these pins (output<n> in the I/O Name column means the n'th bit of output, therefore output<0> should be mapped to F12, output<1> to E12, etc.).

Configuring the Target Device

After completing the mappings, save the changes and close the PACE window to return to the main Xilinx window. You are now ready to place your design on the Spartan 3E. Assure that the USB cable from the Spartan 3E is connected to the computer and click "Configure Target Device" in the processes pane. Your design will be implemented with the specified pin mappings before continuing to the configuration phase.

A prompt will pop-up warning you that no iMPACT project file exists. Select OK. The window below will be displayed:

Assure "Configure devices using Boundary-Scan (JTAG)" is selected and "Automatically connect to a cable and identify Boundary-Scan chain" is selected in the drop-down. Press finish. Xilinx will now connect to the cable to assure it is functioning properly. After this, a select-file window will be displayed. Select the file with the name of your top level component and the ".bit" extension (generally the only file displayed) and press OK. Two more of these windows will pop up. For these, click "Bypass".

Programming the FPGA

Xilinx is now ready to synthesize your design onto the Spartan 3E. Right click the left square in the main pane of Xilinx (should say the name of the .bit file you previously selected under it) and click program to program the FPGA.