Main Page

From FPGA Wiki

Contents 1 Goal of the Project 2 VHDL Preparation 3 FPGA Synthesis 4 References

Goal of the Project

The goal of the project is to synthesize a single-cycle or pipelined version of the MIPS datapath onto the Spartan-3E FPGA.

VHDL Preparation

• Disallowed constructs
• Errors and Overflow

FPGA Synthesis

• Board Setup Tutorial
• Xilinx ISE Tutorial
• Mapping Pins and Programming FPGA
• Custom Clocking
• Button Clock

References

• http://ecen3233.okstate.edu/Fall%202006/PDF/FPGA%20Tutorial.pdf
• http://students.csci.unt.edu/~oba0002/Xilinx.doc
• http://www.xilinx.com/support/documentation/boards_and_kits/ug130.pdf
• http://courses.ece.uiuc.edu/ece443/Breadboard.htm