Errors and Overflow

From FPGA Wiki

In Sonata, errors simply terminate the simulation and overflows wrap around (MAX_INT + 1 will wrap back to 0). When synthesizing code onto the Spartan 3E, issues such as these will cause unpredicable behavior and may not even be noticable.

Indicators of Errors

Errors generally cause some strange behavior when the arise on an FPGA. Generally, it will cause the LEDs to be varying intensities. They can also cause the LCD screen (even if not in use) to flicker slightly. Also, if using a button or switch for input (clock or otherwise), setting that input device to HIGH will sometimes output strange patterns on the LEDs as well.

Numeric Overflow

One consideration when synthesizing the MIPS datapath onto an FPGA is to assure that the program counter will not overflow. If there are no jumps, the PC will overflow in about 20 seconds. There are a number of ways to prevent this but the simplest is to simply limit the maximum value of the PC alltogether. For example, if a program is 100 instructions long, use a conditional to tell the PC that if the write value being sent in is greater than 400 (the last instruction is at 4*100 = 400), to continually output 404. This will cause the PC to loop at instruction 101 forever and never cause overflow.

NOTE: This does require there to be a NOP at the end of the program (instruction 101).

Array Overflow

If a program is 100 instructions long, and the PC is outputting a value of 404 (indicating instruction 101), instruction memory will cause an error. To fix this, simply add a conditional in instruction memory similar to:

if(pc >= instructions'length) then
	output <= X"00000000";
end if;

This will cause any out of bounds exceptions to simply call a NOP.