Button Clock

From FPGA Wiki

One of the more challenging aspects of synthesizing a design onto an FPGA is the fact that the clock, even if modified (as shown here), is much too fast to see each individual instruction execute. To make "stepping through" a program easier, it is possible to map the clock signal of your top-level component to a switch of button on the FPGA.

Mapping the Clock to a Switch

Buttons have shown variability in performance when it comes to acting as a clock as for this tutorial we will map the clock to the right-most switch in the lower right corner of the Spartan-3E.

NOTE: Before proceeding, it is expected that you know how to map pins in Xilinx. For more information see the Mapping Pins and Programming FPGA tutorial.

To start, open the pin mapping editor PACE by selecting the top-level component and then navigating in the lower left "Processes" pane to User Constraints -> Floorplan Area / IO / Logic - Post-Synthesis. Instead of mapping the clock signal to C9, map it to L13.

Re-run the "Implement Design" process. You will receive an error (our input clock at the top level is called clock_signal):

ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
   clock site pair. The clock component <clock_signal_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y1>. The IO component
   <clock_signal> is placed at site <L13>.  This will not allow the use of the fast path between the IO and the Clock
   buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
   in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this
   override is highly discouraged as it may lead to very poor timing results. It is recommended that this error
   condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below.
   These examples can be used directly in the .ucf file to override this clock rule. 
   < NET "clock_signal" CLOCK_DEDICATED_ROUTE = FALSE; >

To allow a switch or button to be used for a clock, the constraints file must be edited to explicitly allow it. Navigate to the file named after your top-level component .ucf and open it in notepad. Ours looks like:

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "clock_signal"  LOC = "L13"  ;
NET "output<0>"  LOC = "F12"  ;
NET "output<1>"  LOC = "E12"  ;
NET "output<2>"  LOC = "E11"  ;
NET "output<3>"  LOC = "F11"  ;
NET "output<4>"  LOC = "C11"  ;
NET "output<5>"  LOC = "D11"  ;
NET "output<6>"  LOC = "E9"  ;
NET "output<7>"  LOC = "F9"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Add the line NET "clock_signal" CLOCK_DEDICATED_ROUTE = FALSE;, replacing clock_signal with the name of the input clock on your top-level component. Afterward, it will look like:

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "clock_signal"  LOC = "L13"  ;
NET "clock_signal" CLOCK_DEDICATED_ROUTE = FALSE;
NET "output<0>"  LOC = "F12"  ;
NET "output<1>"  LOC = "E12"  ;
NET "output<2>"  LOC = "E11"  ;
NET "output<3>"  LOC = "F11"  ;
NET "output<4>"  LOC = "C11"  ;
NET "output<5>"  LOC = "D11"  ;
NET "output<6>"  LOC = "E9"  ;
NET "output<7>"  LOC = "F9"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Back in Xilinx, double click "Implement Design" in the "Processes" pane again. This time there should be no error and you can synthesize as usual.

Note

It should be noted that button and switch clocking should not be used with a custom clock as described in Custom Clocking.